1. Field of the Invention
The present invention pertains to the preparation of semiconductor wafers and in particular to the preparation of wafers for whole (or full) wafer backside analysis.
2. Description of the Related Art
The use of the semiconductor devices in today's commercial goods is undergoing dramatic growth. In order to expand the use of semiconductor devices in lower cost traditional products, semiconductor devices must be produced at previously unattainable low cost. Virtually every step of semiconductor device production is undergoing extensive investigation in an effort to obtain cost savings which will expand the market for semiconductor products. Lowering the cost of semiconductor devices will also enable further progress in state of the art technologies.
It is generally recognized that substantial cost savings can be employed if large scale manufacturing techniques can be brought to bear on whole wafers containing multiple, usually identical, electronic devices that are simultaneously formed on the wafer substrate, prior to the wafer being divided into individual units or dies. It has been found efficient in constructing semiconductor wafers that a substrate of semiconductor material, preferably silicon, receives overlying layers of active devices and inter-layer interconnects. After each layer is formed on the substrate, the frontside surface or active surface of the wafer is planarized or flattened so that succeeding layers are formed with a desired registry and upright orientation. Exceedingly stringent flatness requirements are necessary for small dimensioned patterning. As the layers are built up, one upon the other, a variety of electronic devices are formed on the wafer substrate and typically multiple, identical devices are simultaneously formed in the layer-by-layer operations. Usually, only the active surface or frontside surface of the wafer undergoes extensive flattening, with the reverse or backside remaining free of layering processes and the need for flattening steps. As will be appreciated, the techniques used for layer fabrication and the flattening processes cause stress inducing forces to be stored within the wafer construction. Gross chemical and atomic-level forces are also imparted to the internal structure of the semiconductor wafer and contribute to its loss of mechanical ruggedness.
Following wafer fabrication, the wafer undergoes testing in which individual electronic devices carried on the wafer are electrically tested for proper circuit performance and desired electrical characteristics. In one type of analysis, commonly referred to as a wafer electrical probe or a wafer sort, the wafer is mounted on a vacuum chuck and is indexed to bring different circuit devices into contact with electrical probes connecting the wafer device to external test circuitry. Such wafer electrical probes are typically performed on the frontside surface or active surface side of the wafer with the reverse or backside surface of the wafer lying outside of the area of interest.
With increasing development of semiconductor technology, different types of analyses are being developed. One area of investigation seeks to exploit advantages that can be obtained from reducing the overall thickness of the wafer, by removing inactive material from the backside surface of the wafer. While wafer thinning and aforementioned testing and analysis steps are carried out in individual semiconductor devices (“dies”) formed by dividing the wafer, it is anticipated that substantial cost advantages (due to increased throughput; and relatedly an increased ability to quickly detect, and therefore remedy, process problems, so as to minimize the effect of such process problems, i.e., to minimize the number of wafers that are processed before such process problems are detected) can be obtained if such operations could be carried out on the multiple devices comprising a whole (or entire) semiconductor wafer, before the wafer is divided into individual die. Investigation of whole wafer manufacturing techniques has been seriously curtailed due to practical constraints associated with wafer strength. Due to relatively large wafer sizes and the trend to employ even larger size wafers, it is increasingly important that the wafer be mechanically strong to support its own weight and to withstand the rigors of post fabrication treatments, without cracking or other gross mechanical damage.